• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An operation for writing at least one piece of data into at least one electrically programmable and erasable read-only memory cell comprises at least one step of erasing or programming said cell by a corresponding erasure or deletion pulse. programming. The good or the bad course of the write operation is checked by an analysis of the shape of said erasure or programming pulse (IMPB) during the corresponding step of erasure or programming, the result of this analysis being representative of a correct progress or not of the writing operation.
    公开号:FR3039921A1
    申请号:FR1557576
    申请日:2015-08-06
    公开日:2017-02-10
    发明作者:Francois Tailliet；Marc Battista
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    Method and system for controlling an operation of writing data in a memory cell of the EEPROM type
    Embodiments and embodiments of the invention relate to the electrically programmable and erasable ROMs known as EEPROM memories, and more particularly to the control of the good or bad progress of the write operation. The invention is advantageously but not limited to controlling the level of charge of a power supply means, for example a battery or batteries, supplying an apparatus incorporating one or more of these memories. This is the case for example hearing aids that turn out to be particularly "greedy" in batteries. Also have an indicator of the charge level of these batteries would change only when necessary, especially when the load level does not allow for example a good progress of a write operation in the EEPROM memory.
    According to a mode of implementation and realization, it is proposed a new solution, simple to implement, to detect the good or the bad progress of a write operation in a memory cell of the EEPROM type and thus to provide an indication of a charge level, low or good, of the supply means supplying the memory cell and its associated circuitry.
    An EEPROM memory cell generally comprises a transistor having a floating gate for storing the data, a control gate, a source region, and a drain region. Such a memory cell uses the principle of nonvolatile storage of charges on the floating gate of the transistor. Conventionally, the operation or write cycle of a data comprises an erasure step followed by a programming step.
    The programming is done by Fowler-Nordheim effect using a voltage pulse comprising a ramp followed by a voltage plateau having a high value, typically of the order of 13 to 15 volts, and comprises the tunnel injection of electrons from the floating gate to the drain while the erasure, which is also effected by the Fowler-Nordheim effect, comprises an electron tunneling injection of the drain to the floating gate and is also carried out using an impulse erasing shape similar to that of the programming pulse.
    According to one aspect, there is provided a method of controlling an operation for writing at least one datum in at least one electrically programmable and erasable read-only memory cell, comprising at least one erasing or programming step said cell by a corresponding erase or programming pulse.
    Indeed in some cases depending on the logical value of the data or the word to be written, the write operation may comprise only an erase step or only a programming step.
    Thus, if for example the word to be written contains only "0", then only one erasing step is necessary.
    Similarly, when the word OF (in hexadecimal notation) is to be replaced by the word 1F, the erasure step is unnecessary.
    The method according to this aspect also comprises an analysis of the shape of said erase or programming pulse during the corresponding step of erasure or programming, the result of this analysis being representative of a correct or not the write operation.
    Thus while in the prior art, an EEPROM cell is written in "blind", that is to say that the write operation is non-algorithmic and devoid of control during the write operation itself, the method according to this aspect provides for performing a check during the write operation (clear step or programming step) by analyzing the shape of the corresponding erasure or programming pulse.
    And such an analysis is easier to implement than a conventional control of a correct writing or not predicting, after writing, a reading of the written data with read parameters modified.
    When the write operation comprises the step of erasing followed by the step of programming said cell, the method further comprises an analysis of the shape of each of said pulses during the corresponding step, the result of this analysis being representative of a correct progress or not of the writing operation.
    A nominal erase pulse and / or a nominal programming pulse comprises a ramp followed by a plateau having a nominal voltage, and said shape analysis then advantageously comprises a determination of the duration of said plateau, a plateau having a duration of less than a time limit being representative of an incorrect sequence of the write operation.
    According to an implementation mode, the determination of the duration of said plateau comprises a determination of the instant of occurrence of said plateau and a comparison of this instant of occurrence with a reference moment corresponding to a percentage of the duration of the corresponding nominal pulse, a moment of occurrence less than or equal to the reference time being representative of a correct course of the write operation and a time of occurrence greater than the reference time being representative of an incorrect operation of the write operation. The reference time corresponds for example to 80% of the duration of the nominal pulse.
    According to another aspect, it is proposed to apply the method as defined above, to the control of the charge level of a supply means supplying a memory device containing at least one EEPROM-type memory cell.
    According to another aspect there is provided a memory device, comprising a memory plane containing at least one electrically programmable and erasable read-only memory cell and control means configured to control the progress of a write operation of at least one datum in said at least one memory cell comprising at least one step of erasing or programming said cell by a corresponding erase or programming pulse, said control means including analysis means configured to perform an analysis of the shape of said erase or programming pulse during the corresponding erasure or programming step and issue an indication representative of whether or not the writing operation is correct according to the result of this analysis.
    According to an embodiment in which the write operation comprises the step of erasing followed by the programming step of said cell, the analysis means are configured to perform an analysis of the shape of each of said pulses at during the corresponding step, and issue said representative indication of whether the write operation is correct or not depending on the result of this analysis.
    According to an embodiment in which a nominal cancellation pulse and / or a nominal programming pulse comprises a ramp followed by a plateau having a nominal voltage, the analysis means comprise determination means configured to determine the duration of said plateau, a plateau having a duration less than a time limit being representative of an incorrect operation of the write operation.
    According to one embodiment, the determination means comprise a detection module configured to detect the instant of occurrence of said plateau and comparison means configured to compare this instant of occurrence with a reference time corresponding to a percentage of the duration of the corresponding nominal pulse, a moment of occurrence less than or equal to the reference time being representative of a correct course of the write operation and a time of occurrence greater than the reference time being representative of an incorrect operation of the write operation.
    According to another aspect there is provided an apparatus, comprising a memory device as defined above, a supply means configured to feed the memory device, and means for indicating the charge level of the supply means these indicating means incorporating said control means. Other advantages and characteristics of the invention will emerge on examining the detailed description of embodiments and embodiments, which are in no way limiting, and the appended drawings in which: FIGS. 1 to 6 schematically illustrate various modes of implementation and realization of the invention.
    In FIG. 1, the reference APP designates an apparatus, for example a hearing aid, comprising an ALM supply means, for example a battery or batteries, supplying in particular a non-volatile memory device of the EEPROM type.
    The memory device DIS also comprises MCTRL control means configured, as will be seen in more detail below, for controlling the progress of a data writing operation in at least one memory cell memory plane PM of the memory device, and provide a representative IND indication of the load level of the ALM supply means. The APP apparatus also incorporates MDNCH indicating means, incorporating the MCTRL control means as well as for example a microcontroller, and intended to provide, in the presence of said IND indication, an audible alert for example, in particular one or more "beeps". »Regular using a mini HP speaker.
    In practice, and by way of non-limiting example, as long as the mini speaker is silent, the batteries can not be changed. By cons, when the "beep" or "beeps" are emitted, the ALM batteries are to change.
    In practice, the microcontroller and the mini-speaker are already generally present in a hearing aid and may also be associated with a signal processing processor. In this case it is easy to embed a sound "system" in the auditory content delivered in the ear and said sound alert can be not only one or more "beeps" but also for example a specific sentence of the type "please change the Battery ".
    The memory plane PM of conventional structure and known per se, comprises memory cells CEL EEPROM type.
    An XDCD column decoder and a YDCD line decoder make it possible to address the memory plane PM.
    These decoders are themselves addressed by an ADRG address shift register.
    The memory device DIS also includes a data shift register DRG connected to the memory plane by the XDCD column decoder.
    The addresses and data can be input from the ADRG address register and the DRG data register respectively and the data can be retrieved via the DRG data register.
    The memory device DIS also has an SRG status register connected to the DRG data register. All of these means is controlled by LG control logic.
    Lastly, MGHV high voltage generation means including in particular a charge pump and its associated regulation, make it possible to generate the high voltage, typically of the order of 15 volts, to enable the operation of writing data into the memory , typically having an erase step followed by a programming step.
    It is recalled here that an EEPROM-type memory cell comprises a transistor conventionally having a control gate, a floating gate, a drain region and a source region.
    Such a cell is erasable and programmable by Fowler-Nordheim effect.
    As indicated above, the writing of data in such an EEPROM type cell generally comprises an erasure step preceding a programming step.
    In the erasure step, the drain and the source of the transistor are coupled to ground and a control voltage having an erase value, typically of the order of 15 volts, is applied to the control gate.
    As for the programming of the cell, it is conventionally done by connecting the control gate to ground and applying a programming voltage on the drain, typically also of the order of 15 volts. Regarding the source, either the floating source can be left or preloaded to a non-zero precharge voltage.
    Although an EEPROM memory cell has two main operating modes, namely a read mode and a write mode, the write operation is the first to be defective when the supply voltage Vdd decreases. until you reach a very low level. Indeed, the erase step or the programming step require the internal generation of the high voltage, typically 15 volts, through several stages of charge pump.
    Thus, while the read operation can be functionally correct up to 1.3 volts, the write operation is generally considered correct up to 1.6 volts and can then be downgraded from 1.6 volts to 1.4 volts to be immediately considered defective below 1.4 volts.
    Furthermore, a cell written in a degraded operating mode can be read correctly at time t = 0 and then be defective right after.
    FIG. 2 illustrates a write operation implemented by the use of an erasure pulse IMPI followed by a programming pulse IMP2. The maximum value of the duration of the write operation, substantially equal to the sum of the durations of the IMPI and IMP2 pulses, is included in the memory specifications.
    Each voltage / time pulse has a ramp that controls the tunnel current of the cell, followed by a PLT board, typically at a nominal level of 15 volts.
    FIG. 3 is a zoom of one of the pulses IMP1 or IMP2 and this pulse IMPN represents here a nominal trapezoidal pulse having a plateau of nominal characteristics PLTN. In the nominal case, the duration of the pulse IMPN is fixed, for example equal to 1.5 ms and the duration of the PLTN plateau is for example equal to 1 ms.
    As indicated above, while the write operation generally comprises an erase step followed by a programming step, it is possible, in certain cases, for a single erase or programming step to be necessary. to write a word in memory.
    Thus, if the word to be written contains only "0", then only one erase step is necessary.
    Similarly, when the word OF (in hexadecimal notation) is to be replaced by the word 1F, the erasure step is unnecessary.
    As indicated above, the means for generating the high voltage for generating the IMPI and / or IMP2 pulses comprise one or more stages of charge pumps associated with a charge pump regulation comprising for example an oscillator.
    The regulation controls the output voltage of the charge pump. The oscillator is stopped when the output of the charge pump exceeds a high reference. The output voltage of the charge pump then begins to decrease due to charging. As soon as the output voltage of the charge pump is lower than a low reference, the oscillator restarts. The voltage difference between the low and high references (hysteresis) ensures stability. This voltage difference is for example of the order of 100 millivolts.
    The regulation level of the charge pump is for example the voltage level of the PLT plate, for example 15 volts. The charging ramp is for example generated by an analog integrator which receives as input the plateau voltage.
    The duration of the pulse (ramp + plateau) is controlled by a timer ("timer"), analog or digital. As a guide, a digital stopwatch may include a fixed frequency oscillator connected to a counter. The meter starts when the charge pump starts and the end of the count marks the end of the pulse.
    As is conventional, the programming or erasure pulse, generated by the one or more charge pump stages and the associated regulation, is applied to a circuit having a capacitive load as well as leakage currents.
    When the supply voltage drops, the output of the charge pump drops sharply.
    And when the output of the charge pump is low, its current may for example be less than the current required for the capacitive load, in which case the ramp takes a shape of the type shown in Figure 4, slowing down and taking shape curved, the plateau being naturally shortened.
    When the output of the charge pump is low, its current may also be less than said leakage currents and the rated voltage of the tray is not reached.
    These two alternatives can also cumulate.
    According to one aspect of the invention, it will be controlled whether or not the operation of writing a data in a memory cell or more generally the correct course or writing of at least one word in a memory cell the memory plane PM, by analyzing, during the write operation, the shape of the erase pulse and / or the programming pulse during the corresponding step of erasure and / or programming. In this respect, this shape analysis can advantageously be implemented by determining the duration of the plateau of the corresponding pulse.
    Thus, a tray having a duration less than a time limit is representative of an incorrect operation of the write operation.
    To determine this duration of the plateau, one can for example determine the instant of occurrence of the plateau, that is to say the moment when the ramp ends, that is to say the moment when the level pulse voltage reaches the plateau level.
    And this is possible in particular because the circuitry for generating the erase or programming pulse makes it possible to detect the moment when the plateau is reached, that is to say the moment when the instantaneous amplitude of the Pulse during the ramp reaches the set maximum amplitude limit of the pulse (which is that of the plateau).
    This instant of occurrence can then be compared with a reference time corresponding to a percentage of the duration of the corresponding pulse, for example 80% of the duration of a nominal pulse.
    And, if this instant of occurrence is less than or equal to the reference time, then the progress of the write operation is considered to be correct whereas if this instant of occurrence is greater than the reference time , then the progress of the write operation is considered incorrect.
    This will be illustrated in more detail with particular reference to Figures 4 and 5.
    In these figures, it is considered that it is in the presence of a low power supply situation resulting in a limitation of the charge pump.
    As explained above, the ramp is then slower than the rectilinear ramp of the nominal case and has the shape of a load curve of a capacitive resistive circuit RC.
    In these two figures, treg denotes the instant of occurrence of the plateau and tref denotes the reference time equal to a percentage of the nominal duration of a pulse, for example 80% of 1.5 ms.
    In FIG. 4, it can be seen that the moment of occurrence treg of the plateau PLTB of the pulse IMPB is before the instant tref. In this case, the duration of the PLTB board is considered to be sufficient to ensure correct writing of the word in the memory.
    In this situation, the progress of the write operation is therefore considered to be correct.
    On the other hand, in FIG. 5, the instant of occurrence treg of the PTM plateau of the pulse IMPM is located after the reference time tref.
    Consequently, the duration of the PLTM board is insufficient to ensure that the word is correctly written in the memory and therefore the write operation is considered to have an incorrect sequence. The reference time tref is for example determined at the factory during the phase of characterization of the memory.
    In practice, as illustrated in FIG. 6, the MAL analysis means configured to analyze the shape of the erasure and / or programming pulse comprise an MCM detection module configured to detect the instant treg from the output voltage of the PCH assembly (charge pump + regulation). At this moment, the value of the counter CPT is read and stored for example in a flip-flop.
    A comparator CMP then compares this value of the counter at the reference time tref and then delivers the indication IND representative of a correct or not a proper operation of the write operation.
    This IND indication may be for example a bit taking the value "1" for an incorrect sequence and the value "0" for a correct sequence of the write operation.
    Thus, if, for example, the nominal duration of an erasure and / or write pulse results in a counter having a value equal to 1024, the instant can be considered as being equivalent to a counter value equal to 800.
    The value of the bit IND can be accessible by a bus of the type STI by using for example one of the unused bits of a status word present in the status register SRG.
    This bit IND can be a volatile bit reset to "0" at each stop of the operation of the APP device.
    As indicated above, when the microcontroller associated with the EEPROM detects the presence of an IND bit equal to "1", it can then make the decision to transmit one or more "beeps" and / or a specific sentence via the HP speaker indicates to the user that it is urgent to change the battery. The microcontroller can also make the decision to prohibit any new write command in the EEPROM memory to avoid any malfunction.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. A method for controlling an operation for writing at least one data element in at least one memory cell of the electrically programmable and erasable read-only memory type, comprising at least one step of erasing or programming said cell by a corresponding pulse of erasure (IMPI) or of programming (IMP2) and an analysis of the shape of said erase or programming pulse during the corresponding step of erasure or programming, the result of this analysis being representative whether or not the writing operation is correct.
    [2" id="c-fr-0002]
    The method of claim 1, wherein the write operation comprises the step of erasing followed by the step of programming said cell, the method further comprising analyzing the shape of each of said pulses (IMPI , IMP2) during the corresponding step, the result of this analysis being representative of a correct operation or not of the write operation.
    [3" id="c-fr-0003]
    The method according to one of the preceding claims, wherein a nominal erasure pulse (IMPN) and / or nominal programming impulse (IMPN) comprises a ramp followed by a platter (PLTN) having a nominal voltage, and said shape analysis comprises a determination of the duration of said platen, a platter (PLTM) having a duration less than a time limit being representative of an incorrect sequence of the write operation.
    [4" id="c-fr-0004]
    4. Method according to claim 3, wherein the determination of the duration of said plateau comprises a determination of the instant of occurrence (treg) of said plateau and a comparison of this instant of occurrence with a corresponding reference time (tref). a percentage of the duration of the corresponding nominal pulse (IMPN), a moment of occurrence less than or equal to the reference time being representative of a correct operation of the write operation and a moment of occurrence greater than the reference time being representative of an incorrect operation of the write operation.
    [5" id="c-fr-0005]
    5. The method of claim 4, wherein the reference time is 80% of the nominal pulse duration (IMPN).
    [6" id="c-fr-0006]
    6. Application of the method according to one of the preceding claims, the control of the load level of a supply means (ALM) supplying a memory device (DIS) containing at least one EEPROM type memory cell.
    [7" id="c-fr-0007]
    Memory device, comprising a memory plane (PM) containing at least one electrically programmable and erasable read-only memory cell and control means (MCTRL) configured to control the progress of a write operation of at least one datum in said at least one memory cell comprising at least one step of erasing or programming said cell by a corresponding erasure pulse (IMPI) or programming pulse (IMP2), said control means comprising means for analysis (MAL) configured to perform an analysis of the shape of said erase or programming pulse during the corresponding step of erasure or programming and to provide an indication representative of a correct or unwrought write operation according to the result of this analysis.
    [8" id="c-fr-0008]
    8. Device according to claim 7, wherein the write operation comprises the erasing step followed by the programming step of said cell, and the analysis means (MAL) are configured to carry out an analysis of the shape of each of said pulses during the corresponding step, and provide said representative indication of whether or not the write operation is correct as a function of the result of this analysis.
    [9" id="c-fr-0009]
    9. Device according to one of claims 7 or 8, wherein a nominal erase pulse and / or a nominal programming pulse comprises a ramp followed by a plate (PLTN) having a nominal voltage, and the means of analysis (MAL) comprises determination means configured to determine the duration of said plateau, a plateau having a duration less than a time limit being representative of an incorrect sequence of the write operation.
    [10" id="c-fr-0010]
    10. Device according to claim 9, wherein the determining means comprises a detection module (MCM) configured to detect the instant of occurrence (treg) of said plateau and comparison means (CMP) configured to compare this instant of time. occurrence (treg) with a reference moment (tref) corresponding to a percentage of the duration of the corresponding nominal pulse, a moment of occurrence less than or equal to the reference time being representative of a correct sequence of the writing operation and a moment of occurrence greater than the reference time being representative of an incorrect operation of the write operation.
    [11" id="c-fr-0011]
    11. Device according to claim 10, wherein the reference time corresponds to 80% of the duration of the nominal pulse (IMPN).
    [12" id="c-fr-0012]
    Apparatus, comprising a memory device (DIS) according to one of claims 7 to 11, a supply means (ALM) configured to supply the memory device (DIS), and indicating means (MDNCH) the load level of the feed means, said indicating means (MDNCH) incorporating said control means (MCTRL).
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    法律状态:
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    优先权:
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    FR1557576A|FR3039921B1|2015-08-06|2015-08-06|METHOD AND SYSTEM FOR CONTROLLING A DATA WRITE OPERATION IN A MEMORY CELL OF THE EEPROM TYPE|
    FR1557576|2015-08-06|FR1557576A| FR3039921B1|2015-08-06|2015-08-06|METHOD AND SYSTEM FOR CONTROLLING A DATA WRITE OPERATION IN A MEMORY CELL OF THE EEPROM TYPE|
    CN201610099467.5A| CN106448731B|2015-08-06|2016-02-23|For managing the method and system of the write cycle of the data in eeprom memory unit|
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    US15/055,552| US9455034B1|2015-08-06|2016-02-27|Method and system for managing a writing cycle of a data in a EEPROM memory cell|
    DE102016104343.5A| DE102016104343B4|2015-08-06|2016-03-09|Method and system for checking the writing of a data item in a memory cell of the EEPROM type|
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